Direct-sampling receivers sample a received signal without down-converting the received signal. In contrast, direct-conversion receivers down-convert the received signal to generate in-phase (I) and quadrature (Q) signals, and then sample the I and Q signals. Down-converting the received signal allows for a lower-frequency sampling clock (as compared to direct-sampling receivers), but introduces signal impairments resulting from local oscillator noise and/or I/Q mismatch.
The Nyquist theorem calls for the sampling clock frequency to be at least twice the highest frequency component in the received signal to prevent aliasing. For example, to directly sample signals having a carrier frequency of 197 MHz, a sampling clock having a frequency of at least 2×197 MHz=394 MHz is typically used. Many direct-sampling receivers employ a sampling clock having a frequency that is several times greater than the Nyquist rate to ease the anti-alias filtering requirements. Generating a stable high-frequency sampling clock may be expensive and/or difficult. In addition, as the sampling clock frequency increases, the cost, size, and complexity of analog-to-digital converters (ADCs) employed as sampling circuits also increases.
Thus, although direct-conversion receivers may employ lower-frequency sampling clocks and less complex ADCs than direct-sampling receivers, direct-conversion receivers suffer from signal impairments resulting from I/Q mismatch and local oscillator noise. Accordingly, there is an undesirable trade-off between direct-sampling receivers and direct-conversion receivers. The disadvantages of this trade-off are exacerbated when the received signal has a large channel bandwidth.